Memory is used for storage of data, program code, and/or other information in many electronic products, such as personal computer systems, embedded processor-based systems, video image processing circuits, portable phones, and the like. Memory cells may be provided in the form of a dedicated memory integrated circuit (IC) or may be embedded (included) within a processor or other IC as on-chip memory. Ferroelectric memory, sometimes referred to as “FRAM” or “FERAM”, is a non-volatile form of memory commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which each memory cell includes one or more access transistors. The non-volatility of an FERAM memory cell is the result of the bi-stable characteristic of the ferroelectric material in the cell capacitor(s), wherein the ferroelectric material has multiple stable states.
Ferroelectric memory cells are often fabricated in stand-alone memory integrated circuits (ICs) and/or in logic circuits having on-board non-volatile memory (e.g., microprocessors, DSPs, communications chips, etc.). The ferroelectric memory cells are typically organized in an array, such as folded-bitline, open-bitline, etc., wherein the individual cells are selected by plateline and wordline signals from address decoder circuitry, with the data being read from or written to the cells along bitlines using sense amp circuits. In a typical 1T1C memory cell, a ferroelectric capacitor is coupled between a plateline signal and a source/drain of a MOS cell transistor, the other source/drain is connected to a bitline, and the transistor gate is connected to a wordline control signal to selectively couple the capacitor with the bitline during read and write operations.
The ferroelectric memory arrays are typically constructed in a device wafer along with CMOS logic circuits, wherein the cell transistors are formed concurrently with logic transistors in the device, and the ferroelectric capacitors are constructed in a capacitor layer above the wafer substrate. For example, the construction of the ferroelectric cell capacitors may be integrated into a CMOS fabrication process flow after transistor formation (e.g., after ‘front-end’ processing), and before the metalization or interconnection processing (e.g., before ‘back-end’ processing). In a typical integration of ferroelectric capacitors in a CMOS process flow, transistors are formed on/in a semiconductor body, and a poly-metal dielectric (PMD) layer is constructed over the transistors, including tungsten contacts extending through the PMD level dielectric to the gate and source/drain terminals of the transistors. Ferroelectric capacitors are typically constructed in a first inter-level dielectric layer (e.g., ILD0) above the PMD level, wherein interconnection of the capacitors, transistors, and other components (e.g., signal routing) is provided in one or more metalization layers or levels above the ILD0 level.
One difficulty in integrating ferroelectric capacitors into CMOS process flows is the susceptibility of ferroelectric materials to hydrogen related degradation. Many back-end metalization processing steps include hydrogen, for example, in forming trench etch-stop layers, etch clean operations, copper sintering, and other process steps. For unprotected ferroelectric capacitors, such back-end process hydrogen may diffuse into the ferroelectric cell capacitors, causing degradation in the electric properties of the ferroelectric memory cells, including degraded switched polarization. Diffusion barriers may be provided over patterned capacitor stack structures to help reduce migration of hydrogen into the capacitor material layers. However, conventional hardmask structures used in patterning ferroelectric capacitor stacks suffer from cracking during formation of diffusion barrier layers, and may cause hydrogen diffusion paths. Accordingly, there is a need for hardmasks and methods for forming ferroelectric capacitors that can better protect the ferroelectric capacitors from hydrogen in back-end processing.